The DM4021 is a high-speed T-type flip-flop fabricated using 1μm HBT GaAs technology. The T flip-flop consists of a master-slave latch, closed-in feedback, and is designed using an ECL topology in order to guarantee high-speed operation. The data input may be either AC or DC coupled, the output is DC coupled. At the input side the internal 50-ohm resistors avoid the need for external terminations for impedance matching. The DM4021 uses SCFL I/O levels and is designed to allow for either single-ended or differential data input/output. An on-chip, output buffer produces an excellent eye diagram up to an output rate of 12.5 Gb/s rate (20 Gb/s NRZ or 12.5 Gb/s RZ input data rate) or 14 GHz input clock. The high output voltage, excellent rise and fall times, and the high-quality eye diagram at all clock frequencies makes the DM4021 suitable for very-high-speed, complex digital applications such as differential encoding, clock dividers, and edge detectors.

• Data rate range: 20 NRZ (12.5 RZ) Gb/s
• Maximum clock frequency as clock divider: 14 GHz
• 900 mVpp typical single-ended output
• Input sensitivity: Single ended input >250 mV
• Jitter transfer RMS: <1 ps
• Output rise time (20% - 80%): <27 ps
• Output fall time (20% - 80%): <24 ps
• DC or AC coupled data input
• 50-ohm matched DC-coupled data output
• Differential or single-ended inputs and
• Outputs
  Full SCFL I/O level compatibility
  Low power consumption: 0.71 W
• Available in Plastic QFN4x416L package (upon request) or die

Please download datasheet or our product review (Acrobat Reader needed).

Application Notes