The DM4080 is a high-speed Cascaded T-type flip-flop clock divider fabricated using 1μm HBT GaAs technology. Each T flip-flop consists of a master-slave latch, closed-in feedback, and is designed using an ECL topology in order to guarantee high-speed operation. The data input may be either AC or DC coupled, the output is DC coupled. At the input side the internal 50-ohm resistors avoid the need for exte\rnal terminations for impedance matching. The DM4080 uses SCFL I/O levels and is designed to allow for either single-ended or differential data input/output. The divided by 2 and divided by 4 output are a available at the same time. An additional divided by 4 echo is also provided. This topology makes DM4080 suitable for 2:1 and 4:1 mux selector drivers and clock dividers.

• Maximum clock frequency as clock divider: 12.5 GHz
• 900 mVpp typical single-ended output
• Input sensitivity: Single ended input >300 mV
• Jitter RMS: <1.2 ps
• Output rise time (20% - 80%): <27 ps
• Output fall time (20% - 80%): <24 ps
• DC or AC coupled data input
• 50-ohm matched DC-coupled data output
• Differential or single-ended inputs
• Full SCFL I/O level compatibility
• Power consumption: 1.3 W(@ -5V)
• Available in 5mm QFN Package or diee

Please download datasheet or our product review (Acrobat Reader needed).

Application Notes